The peripheral component interconnect express (PCIe) protocol provides a link training and status state machine (LTSSM) function for managing the state of a PCIe link. The LTSSM monitors packets transmitted/received in a physical layer (PHY) and manages the state of the PCIe link by changing the state between a plurality of operation states (LTSSM states).
In a PCIe switch, the state of the LTSSM at the PHY may transit to an abnormal state and remain in the abnormal state without being returned to a normal state due to, for example, a noise caused by an abrupt removal of a link partner or turning off of a power supply. In this case, since the LTSSM is in an abnormal state, the PCIe switch is unable to operate correctly and fails to inform a software layer of a link down. Further, even though the PCIe switch is supposed to reply an access to a device which has already undergone the link down with an Unsupported Request (UR), since the LTSSM is in an abnormal state, the PCIe switch continuously queues in its buffer. As a result, the buffer becomes full, a blocking occurs, and finally a buffer full state of a central processing unit (CPU), which is a root complex, is caused, which results in a CPU hang up.
FIG. 5 is a diagram illustrating a configuration of a conventional electronic device equipped with a PCIe switch. An electronic device 1000 illustrated in FIG. 5 includes boards 1100 and 1200, and the board 1200 is detachably connected to a connector 1300 of the board 1100. For example, the boards 1100 and 1200 are a controller module (CM) and a channel adapter (CA) of a storage device, respectively. Hereinafter, the board 1100 and the board 1200 may also be referred to as a board #1 and a board #2, respectively.
The board 1100 includes a CPU 1001, a field-programmable gate array (FPGA) 1002, and a switch 1003. The CPU 1001 is a processing device performing various controls and operations. The CPU 1001 is communicably connected with the board 1200 through a switch 1003. The CPU 1001 is provided with a buffer 1011 and data (packet) to be transmitted to the switch 1003 is stored in the buffer 1011. The buffer 1011 includes a plurality of data storage areas, and data (packet) to be transmitted is sequentially stored in the plurality of data storage areas and handled in, for example, a first-in first-out (FIFO) fashion.
The CPU 1001 is connected with the FPGA 1002. The FPGA 1002 is an integrated circuit for which an arbitrary configuration may be set up and implements various functions according to preset settings. For example, when the CPU 1001 falls in a hang up state, the FPGA 1002 outputs a reset signal to the CPU 1001 so as to perform a system reset. The switch 1003 relays a data transfer. The switch 1003 includes a plurality of ports, and devices of data transmission sources and data transmission destinations are connected to the ports. For example, the CPU 1001 is connected to a port of the switch 1003 and a switch 1201 of the board 1200 is connected to another port.
A buffer 1013 is provided in each of the ports of the switch 1003 and stores data transmitted and received through the port. The buffer 1013 of the switch 1003 also includes a plurality of data storage areas, and data to be transmitted is sequentially stored in the plurality of data storage areas and handled in, for example, a FIFO fashion. Hereinafter, for the convenience of explanation, the buffer 1013 of the port connected with a switch 1201 of the board 1200 is referred to as a buffer #1 and the buffer 1013 of the port connected with the CPU 1001 is referred to as a buffer #2, in the switch 1003.
In the CPU 1001, the buffer 1011 of the port connected with the switch 1003 is referred to as a buffer #3. The board 1200 includes the switch 1201 which is connected with the switch 1003 through the connector 1300. Descriptions will be made on a process in which a CPU hang up occurs in the conventional electronic device equipped with a PCIe switch with reference to a flowchart illustrated in FIG. 6.
The board 1100 normally operates in a state of being connected with the board 1200. In this state, it is assumed that the board 1200 is abruptly detached from the connector 1300 (A1). Then, in the switch 1003, the LTSSM state is changed from a normal state to an abnormal state and may remain in the abnormal state without being returned to the normal state (A2). In the switch 1003 of the board 1100, since data is unable to be transmitted to the board 1200, the buffer #1 is filled with data to be transmitted to the switch 1201, which is a disconnected link partner, to become a buffer full state (A3).
In the switch 1003, since data is unable to be transmitted to the buffer #1, the buffer #2 becomes a buffer full state (A4). In the CPU 1001, since data is unable to be transmitted to the switch 1003, the buffer #3 becomes a buffer full state (A5), and the CPU 1001 is hung up (A6).
When the CPU 1001 is hung up, the FPGA 1002 detects the CPU hang up and outputs a reset signal to the CPU 1001 to perform a system reset.
A related technique is disclosed in, for example, Japanese Laid-Open Patent Publication No. 2013-61841.
However, when a CPU reset is performed in the conventional electronic device, it takes time for restart of the device and a downtime becomes longer.